/* this module infers block ram */

// Dual Port Block RAM (True Dual Port, Two R/W Ports)
module dp_bram
(
	clka		,
	dina		,
	addra		,
	wea			,
	douta		,

	clkb		,
	dinb		,
	addrb		,
	web			,
	doutb		
);



/*
parameter WIDTH		= 32;
parameter N_DEPTH	= 1024;
parameter W_DEPTH	=  
		(N_DEPTH <= 2)    ? 1  :
		(N_DEPTH <= 4)    ? 2  :
		(N_DEPTH <= 8)    ? 3  :
		(N_DEPTH <= 16)   ? 4  :
		(N_DEPTH <= 32)   ? 5  :
		(N_DEPTH <= 64)   ? 6  :
		(N_DEPTH <= 128)  ? 7  :
		(N_DEPTH <= 256)  ? 8  :
		(N_DEPTH <= 512)  ? 9  :
		(N_DEPTH <= 1024) ? 10 :
		(N_DEPTH <= 2048) ? 11 :
		(N_DEPTH <= 4096) ? 12 :
		(N_DEPTH <= 8192) ? 13 : 14;
*/
		
parameter WIDTH		= 32;
parameter N_DEPTH	= 1024;
parameter W_DEPTH	= 10; 

input					clka	;
input [WIDTH-1  :0]		dina	;
input [W_DEPTH-1:0]		addra	;
input					wea		;
output reg [WIDTH-1:0]	douta	;

input					clkb	;
input [WIDTH-1  :0]		dinb	;
input [W_DEPTH-1:0]		addrb	;
input					web		;
output reg [WIDTH-1:0]	doutb	;

/* synthesis syn_ramstyle="block_ram" */
reg [WIDTH-1:0] ram [0:N_DEPTH-1];

integer i;
initial begin
	for (i = 0; i < N_DEPTH; i = i+1) begin
		ram[i] = 0;
	end
end

always @(posedge clka) begin
    if (wea)
		ram[addra] <= dina;
	douta <= ram[addra];
end

always @(posedge clkb)
begin
    if (web)
		ram[addrb] <= dinb;
	doutb <= ram[addrb];
end

endmodule
